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SystemVerilog

SystemVerilog

Postby Clams on Sun Jul 14, 2013 10:20 am

The package for SystemVerilog syntax highlighting (and also UCF for xilinx constraint) is available for quite sometime now (in package control and at https://bitbucket.org/Clams/sublimesystemverilog) but I just added a new functionnality: you can now have the declaration of the signal under your cursor (or selected) display in the status bar.
This is extremely basic and can clearly have some issue (especially with port of non-ANSI style module) so if you have any problem please give me some feedback here with example that create issue.
Hopefully I'll stay motivated to enhance this and add more feature to ease writing systemVerilog :)
Clams
 
Posts: 46
Joined: Fri Dec 30, 2011 7:44 am

Re: SystemVerilog

Postby sv_user on Sun Feb 23, 2014 10:49 pm

I just posted this message: viewtopic.php?f=3&t=15452

...there's a bug in the code (regex?) that detects functions. I tried to post an image on the original thread, however it appears the storage quota on this forum has been exceeded and image posting disallowed.
sv_user
 
Posts: 4
Joined: Sun Feb 23, 2014 10:12 pm

Re: SystemVerilog

Postby Clams on Thu Mar 13, 2014 6:12 pm

I just did an update that should fix your issue, and I also added a basic support for typedef struct/enum highlight and symbol (plus a few more uvm type while I was at it :P).
This seems to work reasonably well on my code: when some expression are split between line this make the syntax highlighting a whole more complex to handle and might add a lot of edge effect. Hopefully it is not worse than before :)
As i said in the other thread: do not hesitate to provide patch if you find some things not correctly highlighted, I'm happy to integrate them. And to be sure that I see your message please send a PM since I do not check the forum very often ;)
Clams
 
Posts: 46
Joined: Fri Dec 30, 2011 7:44 am

Re: SystemVerilog

Postby Clams on Thu Mar 20, 2014 6:08 pm

I found some motivation back for this plugin, so I added a simple feature that will generate the instantiation of a module from your project.
It's very basic for the moment (and I'm not entirely happy with the performance to get the list of file ...) but I plan to make this more configurable and with option for auto connection as well as auto declaration.
Feedback more than welcome :)
Clams
 
Posts: 46
Joined: Fri Dec 30, 2011 7:44 am


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