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Re-identation support for VHDL

Re-identation support for VHDL

Postby kedo on Mon Sep 09, 2013 9:23 am

Hi, I am looking for support on re-indentation for VHDL. Something like the "beuatify" feature that xemacs has. Is anyone working on this ?
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Joined: Mon Sep 09, 2013 9:21 am

Re: Re-identation support for VHDL

Postby wltr on Fri Sep 27, 2013 5:09 pm


I'm working on such a plugin trying to add some beautify function and many other features for VHDL (and later hopefully also SystemVerilog). But I basically just started and I guess it will take a while until the first release.

Just check http://vizeda.com every once in a while.

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Joined: Fri Sep 27, 2013 4:46 pm

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