Hi, I am looking for support on re-indentation for VHDL. Something like the “beuatify” feature that xemacs has. Is anyone working on this ?

Hi!

I’m working on such a plugin trying to add some beautify function and many other features for VHDL (and later hopefully also SystemVerilog). But I basically just started and I guess it will take a while until the first release.

Just check vizeda.com every once in a while.

Best,
-J.