Hey all. I don’t know much about regex, but this tool looks like it would be perfect for aligning verilog port lists. Could anyone help me figure out how to configure it to turn code like this:
input [17:0] SW, // write enable, write address, input data
input [0:0] KEY, // reset
input CLOCK_50, // 50 MHz clock
output [0:0] LEDG, // write enable
output [0:6] HEX7, // write address
output [0:6] HEX6, // write address
output [0:6] HEX5, // data in
output [0:6] HEX4, // data in
output [0:6] HEX3, // read address
output [0:6] HEX2, // read address
output [0:6] HEX1, // data output
output [0:6] HEX0, // data output
output [17:0] LEDR // switches
into code like this:
input [17:0] SW , // write enable, write address, input data
input [0 :0] KEY , // reset
input CLOCK_50, // 50 MHz clock
output [0 :0] LEDG , // write enable
output [0 :6] HEX7 , // write address
output [0 :6] HEX6 , // write address
output [0 :6] HEX5 , // data in
output [0 :6] HEX4 , // data in
output [0 :6] HEX3 , // read address
output [0 :6] HEX2 , // read address
output [0 :6] HEX1 , // data output
output [0 :6] HEX0 , // data output
output [17:0] LEDR // switches
Thanks.