Sublime Forum

SystemVerilog language plugin bug (function names after ws)

#1

The following SystemVerilog code demonstrates valid use of cosmetic whitespace in a function definition:

function int
this_function_is_not_recognised();

// Function content…

endfunction

…however, the Sublime Text (+SystemVerilog plugin) does not consider this function name when using Ctrl+R - in this case, the function is incorrectly picked up as “int”.

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SystemVerilog
#2

If you are using a plugin for highlighting SystemVerilog code, it’s the plugin’s fault and not Sublime’s. Well, directly speaking at least.

I see that there is a problem with the syntax definition and I also see why this is prolematic to parse as a regular expression, which ST limits you on, but there is a way to match this kind of function splitting, even if not “perfectly”.

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#3

SystemVerilog is not whitespace-sensitive - in general, I believe all tokens can be separated by arbitrary whitespace (i.e. any number of spaces, tabs or newlines).

I was hoping the plugin author would be able to make a quick fix for this issue (and potentially update the other regexs as well), however if I find some time I’ll investigate the procedure, however I’m new to Sublime Text, so I’ll need to get up to speed with the revision control system used, the local install/build/test procedure, etc first…

Unless, of course, someone else beats me to it.

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#4

I’ve taken a look at the language definition file and even from a cursory inspection I can see a number of bugs (also confirmed by real-world source code samples that fail to highlight or context-search correctly). I’m now in two minds whether it’s worth trying to fix the original file or write a new one.

It also appears that many of the language definition tutorials found online are out of date (referring to JSON instead of YAML, etc).

If I find time, I’ll fix it, but I was hoping for something that worked out the box and not having to jump through hoops.

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#5

Yes, the updated YAML syntax docs have not been merged to the main branch but to the ST2 branch. I have no idea why this was even considered and I aim to merge these more or less myself, if I have to, but I don’t have time for that currently. You can find the YAML docs here.

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#6

I’m maintaining the verilog syntax and I’m fully aware that there is lot of things that could be improved: if you have modification please update the existing one and do some pull request so that everyone benefits from your change :smile:

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