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SystemVerilog

SystemVerilog

Postby Clams on Sun Jul 14, 2013 10:20 am

The package for SystemVerilog syntax highlighting (and also UCF for xilinx constraint) is available for quite sometime now (in package control and at https://bitbucket.org/Clams/sublimesystemverilog) but I just added a new functionnality: you can now have the declaration of the signal under your cursor (or selected) display in the status bar.
This is extremely basic and can clearly have some issue (especially with port of non-ANSI style module) so if you have any problem please give me some feedback here with example that create issue.
Hopefully I'll stay motivated to enhance this and add more feature to ease writing systemVerilog :)
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Re: SystemVerilog

Postby sv_user on Sun Feb 23, 2014 10:49 pm

I just posted this message: viewtopic.php?f=3&t=15452

...there's a bug in the code (regex?) that detects functions. I tried to post an image on the original thread, however it appears the storage quota on this forum has been exceeded and image posting disallowed.
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Re: SystemVerilog

Postby Clams on Thu Mar 13, 2014 6:12 pm

I just did an update that should fix your issue, and I also added a basic support for typedef struct/enum highlight and symbol (plus a few more uvm type while I was at it :P).
This seems to work reasonably well on my code: when some expression are split between line this make the syntax highlighting a whole more complex to handle and might add a lot of edge effect. Hopefully it is not worse than before :)
As i said in the other thread: do not hesitate to provide patch if you find some things not correctly highlighted, I'm happy to integrate them. And to be sure that I see your message please send a PM since I do not check the forum very often ;)
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Re: SystemVerilog

Postby Clams on Thu Mar 20, 2014 6:08 pm

I found some motivation back for this plugin, so I added a simple feature that will generate the instantiation of a module from your project.
It's very basic for the moment (and I'm not entirely happy with the performance to get the list of file ...) but I plan to make this more configurable and with option for auto connection as well as auto declaration.
Feedback more than welcome :)
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Re: SystemVerilog

Postby Clams on Fri Oct 31, 2014 3:12 pm

Slowly but surely, more features are added (version 1.2.0, should be available in PackagControl): now some basic autocompletion for variable method of type array, string, mailbox, semaphore.
The function to display a variable type should also be more reliable, support more coding style and extract only the usefull information.

Next step: support autocompletion for user define type (struct/enum at first and later function/module IOs, class members/methods).
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Re: SystemVerilog

Postby Clams on Mon Nov 10, 2014 10:13 am

I made another significant update around autocompletion and module instantiation:
- Autocompletion now works with interface (providing list of signal of the interface). Also added a few uvm_ functions, system task and macro command
- module instantiation: can now auto-declare signals (if not already exisiting) for automatic connection.

Since these features relies heavily on more or less complex regex I expect it to not work for everyone: if you find some coding style that are parsed properly you can use the issue tracker of BitBucket to provide me some examples.
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Re: SystemVerilog

Postby Clams on Tue Nov 18, 2014 10:23 am

Motivation still high to develop this plugin: there is now an alignment feature for port declaration and module instantiation.
If anyone need more configurability for the alignment style, do not hesitate to ask here or on BitBucket issue tracker.
It is still far from the verilog mode of Emacs, but it's getting there (at least for the feature I liked :P).
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Re: SystemVerilog

Postby gotcha on Tue Nov 25, 2014 7:33 pm

Very good plugin :)
Can you describe your workflow? What simulator do you use and how?
Internally there are lots of regexp, did you try pyparsing?
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Re: SystemVerilog

Postby Clams on Tue Nov 25, 2014 8:42 pm

Thanks :)

In term of workflow, i'm very limited by my work environment where i cannot run sublime in the same environment as the simulator (Questa). So i have some special plugin with one command that save all file, commit to a temporary branch (if not already in a tmp branch) and then push to a private repo accessible in the simulation environment ...

I had a look at pyparsing, mainly with the idea of doing some linting (since i cannot use the output of my simulator to do it), but it feels like a lot of work to start having something working. So that's why i over-abused regexp, it allows me to get features really quickly: i wonder what is the impact in term of performances compare to use a parser and build an AST. In term of parser i also had a look at pydsl which seems pretty interresting.

By the way i added a few new interresting features:
* Expand/compress of .* in module instantiation ala emacs Autostar
* smart always snippet (more configurable and with auto clock/reset name based on context)
* Goto driver, when you want to know who is driving your signal (input of your module, output of an instance, an assign , ...)
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Re: SystemVerilog

Postby gotcha1 on Wed Nov 26, 2014 10:06 pm

Author of the pyparsing wrote grammar for verilog 95.
But the pyparsing module can be used just as object based regexp (easier to understand, make revisions).
Yeah, a full-fledged preprocessor and parser need a lot of time investment.
For performance issue, I think it should be cache for parsed files, with checking timestamp\sha.

Would be nice to see your usecases (wiki\screenshots).
Do you use any test\debug environment for your plugin?
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