Sublime Forum

SystemVerilog

#10

Author of the pyparsing wrote grammar for verilog 95.
But the pyparsing module can be used just as object based regexp (easier to understand, make revisions).
Yeah, a full-fledged preprocessor and parser need a lot of time investment.
For performance issue, I think it should be cache for parsed files, with checking timestamp\sha.

Would be nice to see your usecases (wiki\screenshots).
Do you use any test\debug environment for your plugin?

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#11

I plan to write some doc/example to demonstrate the different feature;)
For the testing of the plugin, unfortunately I do nothing, except use the plugin myself everyday ^^

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#12

I finally found some time to document a bit more seriously the plugin: sv-doc.readthedocs.org/en/latest
I start to have a lot of feature, and many might go un-notice so hopefully this will help people use the plugin to its full capabilities.

I have also compiled the different video available in the docs into a youtube playlist: http://www.youtube.com/watch?v=(https://www.youtube.com/playlist?list=PLv7nwCTbMrd3obnLMeI07wrhciaPlsrgz)

By the way I continued to improve the alignement (now works on assignement, signal declaration, case list) autocompletion (auto-case, auto-modport, scope completion) and added some new feature like FSM template and displaying the hierarchy of a module (all its sub-module)

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#13

That’s really cool! Thanks for your work :smiley:
Do you use any supplementary plugins?

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#14

Very nice plugin; I’m using it daily. I wasn’t aware of the alignment feature, and have been using the excellent AlignTab plugin, but will look at your alignment features too.

Thanks!

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#15

Thanks :smile: The alignment part is still not where I want it to be (ultimate goal: complete beautifier :stuck_out_tongue: ) but it’s slowly progressing: I recently added the indent part even though it does not handle properly all coding style …
Feedback on stuff that does not work or stuff you would like to see is more than welcome :wink:

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#16

Hi,

Thanks for your great SystemVerilog package! I just want to know, I am remotely using questasim and I am using it in Batch mode. Every time that I want to compile my file I have to update the pervious version in the server and run make file. I know that there is build option in Sublime but I am not quite sure how to use it?

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#17

The way to handle that is to have a remote script that you can execute through ssh (check stackoverflow.com/questions/3050 … te-machine) and in Sublime Text you create a new build System (Tool->Build System->New Build System). Just put the ssh command to execute the remote script in the shell_cmd, or better a script doing the ssh command plus the display of the result.

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#18

mo_askar,
ssh session is the best choice, any new ideas you can add here
bitbucket.org/Clams/sublimesyst … n-modelsim

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#19

Since i asked for a tooltip API and there is now one, I had to use it :stuck_out_tongue:
The show info command (F10 in the keybinding example) now use the tooltip by default. I use the color scheme to setup the color used in the tooltip (I looked at what Faceless did with his scopeHunter plugin).
I now need to use it for other stuff (like function for example), but this is already pretty useful :smile:

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#20

I made a significant update:

  • alignment part has been reworked with the main functionality in a file that can be used as stand-alone, outside of ST3: it now properly indent many different styles, and alignement support also more cases.
  • For those using latest dev version, I start using the new syntax highlight. For the moment I only added the highlight of unmatched closing parenthesis/bracket and rework the highlight of typedef which should work a lot better.
  • The Find Instance function has been improved in term of performances and the result now works like the Find In files result where you can simply double click to navigate.

And for information I uploaded my color-scheme to the bitbucket download section: bitbucket.org/Clams/sublimesyst … t2.tmTheme

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#21

[quote=“mpr90”]Very nice plugin; I’m using it daily. I wasn’t aware of the alignment feature, and have been using the excellent AlignTab plugin, but will look at your alignment features too.

Thanks![/quote]

Check all features in the documentation with video examples sv-doc.readthedocs.org/en/latest/

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#22

Anyone having issues with the reindent with lines that are just comments?

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#23

Can you post an example of your problem ?

Edit: The best way is to post your issue (code example+description of what you expect and what really happen) on the github repo, this way I will get a notification :wink:

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#24

Hello!

Thank you for the plugin, it is very useful for my work
But what about coding style - how to change it:
for example
always_ff @(posedge clk) begin : bla

end

I want to change to:
always_ff@(posedge clk)
begin : bla

end
Is any possibility of such trick exist?

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#25

Have you tried setting sv.indent_style to gnu ? Or you also don’t want indentation for the begin keyword ?

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#26

I’m still maintaining this plugin and I had some fun with the use of phantoms to provide a nice side-bar to explore hierarchy (class/module), so I though I would share it here, it could maybe inspire other plugin developers:


The +/- are phantoms and the sub-hierarchy is expanded on click when it is the first time, and after that it becomes a simple fold/unfold

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#27

That’s pretty cool. I was working towards a “speedbar”-like hierarchical display, to the point of having a method to map out an entire directory’s contents of modules/entities/instantiations but then I got stuck with the actual implementation in Sublime.

Are you using Sublime’s object detection here, or do you have something that scans and caches files and locations throughout?

And actually would it be worth spinning this out into a separate HDL outliner package? I would be more than happy to contribute on the VHDL side of the world (my Verilog-fu is meh. I get by but I’m not an expert.)

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#28

I’m using a mix of Sublime’s symbol indexing and some manual parsing of file for a few stuff (like module ports).
The fact that I display sub-level only on-demand allows to keep things simple, I basically juste need to parse manually one file, so no need to cache, and since i’m looking only for a limited amount of stuff it’s easy to do with regexp.

Since I rely on sublime’s indexing, it might not be really clean to have this in a separate package from the syntax, but on the other hand it could allow a multi-language side-bar which would actually be great.

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#29

Okay. Yeah if it’s just within a single file, that’s far easier to do with Sublime’s symbol tools. My script basically indexed an entire tree with file and position. I had a lot of trouble with regex for Verilog instantiations because really gargantuan instantiations would cause catastrophic backtracking. I ended up having to strip out parenthesis interiors which ended up making the regex’s faster even though it’s a hack.

However it did scan an entire project directory tree with mixed Verilog, SystemVerilog (these were mainly IP from Quartus regarding the processor system) and VHDL and created a tree in about 4 seconds – smaller projects are pretty much instantaneous – so even if a hack I was generally pleased with it.

I just couldn’t figure out what to do with it AFTERWARDS because I got very fixated on using the sidebar as an outline. I guess you must keep a mapping in your panel between cursor location and file location. Also folding was very frustrating to work with in Sublime. I don’t remember exactly what the issue was, maybe it was the inability to mark code spots for folding rather than basing it all on indentation.

Unfortunately, we’re getting phase 2 of our boards in … probably T minus 20 minutes now and all hell is going to break loose at that point. I’m going on vacation next week so I’ll probably have some time to browse your repository and see how you do your panel mapping.

If my stuff is at all interesting, I have it stashed in https://github.com/Remillard/HDL-Outliner/blob/develop/hdl_outline.py. I’d started that project but it’s been dormant for awhile as I was out of ideas and time at the time. There’s a sample project output of this big project in the test directory in that same git project. I was styling it like Emacs Speedbar, but that only ever indexed VHDL and mine does everything I think.

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